The present invention relates to manufacturing processes for integrated circuits which include one or more insulated gate field effect transistors with vertical current flow ("power IGFETs" or "power MOS devices"), possibly in combination with other devices.
The manufacturing process for a power IGFET involves a series of operations, including epitaxial growth of an N- silicon layer on an N+ monocrystalline silicon substrate, surface oxidation of said layer for formation of the field oxide, definition of the deep body region and the active areas of the device, growth of a gate oxide layer, deposit and doping of a polycrystalline silicon layer and definition of the gate, body and source regions..sup.1 FNT .sup.1 See, e.g., B. J. Baliga, MODERN POWER DEVICES (1987), POWER INTEGRATED CIRCUITS; PHYSICS, DESIGN, AND APPLICATIONS (ed. Paolo Antognetti, 1986); all of which are hereby incorporated by reference.
One frequent shortcoming is the presence in the gate oxide of the finished device of fractures ("pinholes"), which cause deviations because they generate short circuits between the gate polycrystalline silicon and the body and source regions below. Short circuits can also be generated between the gate polycrystalline silicon and the type N epitaxial layer underlying the gate oxide, thus causing short circuiting of the gate with the drain.
The present invention advantageously avoids this shortcoming by providing a process with reduced danger of short circuits between gate and source of the device.
The disclosed invention provides a process wherein the operations of definition and diffusion of the body and source regions are performed before deposit of the gate polycrystalline silicon layer.